This invention is generally related to input/output (i.e., I/O) circuits and in particular to receiver circuits that perform an equalization process to reduce inter-symbol interference when detecting transmitted symbols.
I/O circuits act as the interface between different logic functional units of an electrical system. The functional units may be implemented in separate integrated circuit dies (i.e., IC chips) of the system. These chips may be in separate IC packages that have been soldered to a printed wiring board (i.e., PWB). The chips communicate with each other over one or more conductive transmission lines. The transmission lines may be a parallel bus formed on a PWB, and they may be of the point-to-point or multi-drop variety. Alternatively, the transmission line may be a serial link such as a coaxial cable. In both cases, each chip has an I/O circuit that includes a driver and a receiver for transmitting and detecting symbols. The driver and receiver translate between on-chip signaling and signaling that is suitable for high speed transmission (e.g., at several hundred megabits per second and higher) over a transmission line. In a xe2x80x98bidirectional linkxe2x80x99, the driver and receiver pair are connected to the same transmission line.
A problem with high speed transmission is that the non-idealities of the line cause the transmitted signal to be distorted by the time it has reached the receiver. This distortion causes the value of a symbol (which may be a sequence of one or more digital bits) detected by the receiver to not be the same as the symbol value that was transmitted by the driver. This distortion is also known as inter-symbol interference (i.e., ISI), where the effect on the detected symbol may in part be caused by adjacent symbols that were transmitted just before and just after the symbol being detected.
To correct for ISI, a feedback control process known as digital equalization may be used. In such a technique, the received transmission line analog signal is first digitized at a very high sampling rate (which is significantly higher than the bit transmission rate). This digitized signal is then fed one sample at a time to a decision feedback equalizer (i.e., a DFE). The DFE subtracts an estimated, digital correction value from a current sample value of the received signal, to yield a more accurate signal value. This corrected signal value is then translated to a logic value, e.g., xe2x80x981xe2x80x99 or xe2x80x980xe2x80x99, by making a comparison with a reference value. Each estimated correction value is determined by a digital filter, based upon previous comparison output logic values. The characteristics of this filter may be xe2x80x98adaptedxe2x80x99, for instance during a training period, so that the comparison output logic values correctly yield the transmitted logic values of a known sequence. That is, the output logic values and the transmitted logic values have been xe2x80x98equalizedxe2x80x99. Thus, the DFE translates a sequence of many digitized samples of a received transmission line analog signal, into a few logic values. This resulting sequence of logic values will define received symbols with improved accuracy, i.e., with lower ISI.